1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an etching method for forming a conductive film pattern on a thin dielectric film having a thickness of 5 nm or less.
2. Description of the Related Art
In recent years, the microfabrication and integration of a semiconductor device has been increasingly enhanced, and a technique for carrying out a processing in a subquarter micron with high precision and reproducibility has been required.
For example, there has been proposed a method which is intended for forming a polycrystalline silicon film on a gate oxide film to be a dielectric film with high precision and uses a first etching method having a high etching rate and a second etching method having a high selective ratio to an oxide film to be a substrate in consideration of the damage of the oxide film such as shown in paragraph 15 of Japanese unexamined patent publication JP-A-9-69511.
In this method, it is assumed that a vertical etching shape can be obtained without etching an insulating layer to be a lower layer, and furthermore, a residue can be completely eliminated in a step portion. In this case, a gate oxide film has a thickness of approximately 20 nm at most.
However, the thickness of the gate oxide film is increasingly decreased. In particular, a gate oxide film having a thickness of 5 nm or less has recently been proposed. In the case in which an MOSFET is to be formed by using such a thin gate oxide film, a silicon type conductive film such as a polycrystalline silicon film formed on an upper layer is subjected to patterning, thereby forming a gate electrode. By using the gate electrode as a mask, an impurity ion for forming source and drain regions is implanted.
Conventionally, an etching step for patterning the polycrystalline silicon film has been executed by using an ECR plasma etching device shown in FIG. 1.
The ECR plasma etching device comprises a quartz window 102 fixed to an upper part in a chamber 101, a lower electrode 103 on which a substrate to be processed is provided, a vacuum pump (not shown) for evacuating air from the chamber 101, and a gas supply system (not shown) for supplying a desirable reactive gas into the chamber 101. A plasma is generated by a microwave having a frequency of 2.45 GHz which is introduced into the chamber 101 through the quartz window 102. 104 and 105 denote coils provided for generating a plasma having a high density by an electronic cyclotron resonance. A positive ion in the generated plasma is incident almost vertically on the substrate to be processed by a self-bias voltage induced to the lower electrode 103 by a high-frequency wave supplied from a high-frequency power source 107 through a high-frequency matching device 108 to the lower electrode 103. Consequently, vertical patterning can be carried out.
FIG. 5 shows a TEM photograph of an etching surface in the case in which a polycrystalline silicon film is subjected to patterning with a Cl2/O2 gas to be a reactive gas by using the ECR plasma etching device. The polycrystalline silicon film is formed on a gate oxide film comprising a silicon oxide film having a thickness of 2.75 nm. Moreover, FIGS. 6(a) and 6(b) show the enlarged photographs of the surface of the polycrystalline silicon film and that of the gate oxide film which are taken at this time, respectively.
In this case, an etching residue remains to draw a wavy pattern on the surface and the surface has a concavo-convex shape as is apparent from FIGS. 5 and 6.
It is apparent that the concavo-convex portions of the surface variously influence subsequent steps.
For example, in some cases in which a complicated impurity diffusion profile is to be formed, particularly, the case in which shallow source and drain regions are to be formed or the case in which source and drain regions having an LDD structure in a very small diffusion depth are to be formed, the condition of the surface of a substrate exposed from a mask greatly influences the profile of an ion to be implanted and a characteristic is varied.
Moreover, there has also been proposed a device having a multilayer structure in which an amorphous silicon film or a polycrystalline silicon film is provided on a gate oxide film thus formed, the polycrystalline silicon film and the amorphous silicon film are annealed, and recrystallization is carried out by using, as a seed, a silicon substrate exposed from a window formed partially, thereby forming a single crystal layer, and a device is formed in the single crystal layer. However, the polycrystalline silicon film formed on the concavo-convex surface successively maintains the exact surface condition. For this reason, it is very hard to form a single crystal layer of high film quality.
In the case in which a film formed on a thin dielectric film is to be patterned, thus, there is a problem in that the surface of the dielectric film formed on a substrate becomes rough. In some cases, this causes various drawbacks in the formation of a device.
Therefore, various experiments and investigations were made. As a result, it was found that in the case in which a silicon type conductive film having a grain boundary such as a polycrystalline silicon film is to be patterned on a dielectric film, the protruded portion of silicon oxide (bulged silicon oxide) is formed on the surface of the silicon oxide provided under the grain boundary of the silicon type conductive film to be the upper layer.
FIG. 7 shows a mechanism for generating the bulge of the silicon oxide film. In a grain boundary portion G of the polycrystalline silicon, the surface is concaved. Therefore, the gate oxide film is locally thinned immediately before the polycrystalline silicon film disappears from the surface of the substrate (a local thinned region L is formed, FIG. 7(a)). According to a model of Cabrera-Mott related to the natural oxide film growth of the surface of the silicon substrate such as shown in Non-patent publications of “Formation of Very Thin Silicon Oxide Film and Interface Evaluating Technique” written by Shigeru Nomura and Ei Fukuda, Realize Co., Ltd.”, or N. Cabrera and N. F. Mott, Rep. Prog. Phys., 12, 163 (1949). JP-A-9-69511, the growth rate of an oxide film depends on a difference in an electric potential which is generated on both ends of the oxide film and is rapidly reduced with an increase in the thickness of the oxide film. The reason is that ionized oxidation species or atoms constituting the substrate drift into the oxide film, resulting in the formation of an oxide film.
In a weak spot W in which the thickness of the oxide film is reduced, accordingly, the oxidation rate of the substrate is lower than that in other portions so that an island I of silicon oxide is formed as shown in FIG. 7(c). This can be supposed to be the bulge of the silicon oxide film. If an oxygen plasma is used in place of a Cl2/O2 plasma, the bulge of the silicon oxide film is not generated. If Cl2 is added at a rate of 21% for O2, the bulge of the silicon oxide film is formed. It has been found that the bulge of the silicon oxide film also becomes remarkable with an increase in a Cl2 concentration.
FIG. 8 shows a result obtained by changing the thickness of a silicon oxide film to measure the amount of an increase in the thickness of the silicon oxide film on a surface thereof. Curves a and b indicate the amount of an increase in the thickness of the silicon oxide film and the final thickness of the silicon oxide film, respectively. An axis of abscissa indicates the initial thickness of the silicon oxide film. From this result, it is apparent that the thickness of the silicon oxide film is more increased with a decrease in the initial thickness from 4 nm.
From this drawing, it is possible to easily estimate that the increase in the thickness of the oxide film in a part of the silicon oxide film becomes great and the oxide film is grown like an island in the case in which the same portion is thinned (locally) at a first etching step.
In many cases, the roughness of the surface adversely affects a device characteristic as described above. For this reason, there has been desired an etching method capable of smoothing a surface and carrying out etching with high pattern precision.